One type of signal processing typically associated with high-density magnetic recording channels is time-domain equalization. Such equalization is used to reshape a readback signal received by the channel to an approximation of a desired target waveform in the time domain, such as used in a Partial Response, Maximum Likelihood (PRML) detection read channel. As will be recognized, reshaping the readback signal allows intersymbol interference (ISI) to be reduced and controlled, facilitating reliable sequential decoding of the digital information stored on disc.
A second type of signal processing typically used in a magnetic recording channel is self-synchronization, which involves synchronization of the rate of data recovery with the rate of incoming readback signal, which varies as a result of the variations of a speed of rotating disc and radial position of the associated head. Typically, such self-synchronization is achieved through the use of a Phase Locked Loop (PLL) frequently referred also as a Phase Locked Ocsillator (PLO) or as a Voltage Controlled Oscillator (VCO), which generates clock signal for the sampling of equalized signals at appropriate moments and for subsequent recovery of the stored data from the samples.
Practical implementations of both equalization and self-synchronization are discussed, for example, in U.S. Pat. No. 5,422,760 entitled "Disc Drive Method Using Zoned Data Recording And Prml Sampling Data Detection With Digital Adaptive Equalization", issued Jun. 6 1995 to Abbott et al and in the paper by Cideciyan et al entitled "A PRML System for Digital Magnetic Recording", IEEE Journal on Selected Areas in Communications, vol. 10, no. 1, Jan 1992. Additionally, for detailed discussion of self-synchronization see U.S. Pat. No. 5,459,757 entitled "Timing And Gain Control Circuit For A PRML Read Channel," issued Oct. 17, 1995 to Minuhin et al. and U.S. Pat. No. 5,854,717 entitled "Self-Synchronization in a Magnetic Recording Channel Utilizing Time-Domain Equalization," issued Dec. 29, 1998 to Minuhin (Minuhin '717), both of which are assigned to the assignee of the present invention.
As taught by these references, self-synchronization is derived from the equalized signal at the output of the equalizer. The basis for this approach is discussed by Mueller's and Muller's in the paper entitled "Timing Recovery in Digital Synchronous Data Receivers", IEEE Transaction on Communications, No.5, May 1976, pp.516-531. It is significant to note that although this approach to self-synchronization was directed toward a digital communication channel and was not developed specifically for magnetic recording channels, practical analog and digital magnetic recording channels utilizing time domain equalization usually use this approach.
Significant limitations, however, have been encountered in the application of the Mueller's and Muller's approach to self-synchronization in magnetic recording channels.
First, the procedures for equalization and self-synchronization are interdependent; that is, to achieve optimal equalization, one needs to employ a clock having an optimal phase (for a given analog input signal), while to derive a clock with an optimal phase one needs an optimally equalized signal.
Second, actual timing error signal for the PLL from the output of the equalizer is corrupted by both the residual equalization error that results from imperfect equalization and by the filtered noise. For certain pattern combinations, the residual equalization error can be indistinguishable from the systematic timing error, so that PLL can be incorrectly driven out of correct phase (and further, for especially "bad patterns", the PLL can be made to lose lock altogether).
Third, in practice, time-domain equalization usually requires a high frequency boost and large mismatch between the target shape and the original "head/media" signal. As a result, significant noise enhancement occurs at the output of the equalizer that further corrupts the timing signal.
Fourth, the locking range of a timing error sensor circuit for sampled signals is generally small, so that in a noisy environment, the PLL may be additionally prone to lose lock.
Finally, in the case of the use of digital equalization, the analog to digital converter (A/D), the equalizer and the signal processing circuit employed to calculate timing error are inside of the PLL. The associated delays from these hardware units result in so-called "transportation delay" or "dead time" which adversely affect the performance and stability of the PLL.
As a result of these and other limitations, there is a need for an improved approach to self-synchronization in a sampled magnetic recording channel which overcomes the deficiencies of the prior art. In addition, a need exists for a solution which enables self-synchronization utilizing relatively low-complexity and low power-consuming circuitry. Also, this solution preferably will provide self-synchronization in a manner such that delays associated with time-domain equalization of readback signal and signal processing delays in data recovery do not affect performance of the PLL. Finally, this solution preferably will provide lock limits that are significantly greater than those used in a prior art, facilitating more reliable operation of the PLL.
The present invention provides a solution to this and other problems, and offers other advantages over the prior art.